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AS1539/AS1541
8 / 4 - C h a n n e l , 1 0 - B i t I C A n a l o g - t o - D i g i ta l C o n v e r t e r
D a ta S he e t
1 General Description
The AS1539/AS1541 are single-supply, low-power, 10-bit data acquisition devices featuring a serial IC interface and an 8-channel (AS1539) or 4-channel (AS1541) multiplexer. The analog-to-digital (A/D) converters features a sample-and-hold amplifier an internal asynchronous clock and an internal reference. The combination of an I C serial, 2-wire interface and micropower consumption makes the AS1539 and AS1541 ideal for applications requiring the A/D converter to be close to the input source in remote locations and for applications requiring isolation. The device is available in a TSSOP-16 or TQFN 4x4 16pin package.
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2 Key Features
! ! ! ! ! ! ! ! !
Single Supply: 2.7 to 5.25V 8-Channel Multiplexer (AS1539) 4-Channel Multiplexer (AS1541) Sampling Rate: 50kSPS No Missing Codes Internal Reference: 2.5V High Speed I C Interface at 3.4MHz <1.5A Full Shutdown Current TSSOP-16 or TQFN 4x4 16-pin Package
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3 Applications
The device is ideal for voltage-supply monitoring, isolated data acquisition, transducer interfaces, batteryoperated systems, remote data acquisition or any other analog-to-digital conversion application. Figure 1. Block Diagram
CH0 CH1 CH2 CH3 CH4 CH5 AS1539 only CH6 CH7 COM 8-Channel MUX Sample/ Hold Amp
Successive Approximation Register Serial Interface
SDA
SCL A0 A1
AS1539/AS1541
CDAC
Comparator
REFIN/OUT
Buffer
Internal 2.5V Reference
GND
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AS1539/AS1541
Data Sheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
+VDD
SDA
CH0
N/C
CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8
16 +VDD 15 SDA 14 SCL CH1 CH2 CH3 N/C 1 2
16
15
14
13 12 SCL 11 A1
AS1539
13 A1 12 A0 11 COM 10 REFIN/OUT 9 GND
AS1541
3 4 5 N/C 6 GND 7 REFIN/OUT 8 COM
10 A0 9 N/C
Pin Descriptions
Table 1. Pin Descriptions AS1539 1:8 9 10 11 12 13 14 15 16 AS1541 1:3,16 6 7 8 10 11 12 13 15 4, 5, 9, 14 Pin Name CH0:CH3 CH0:CH7 GND REFIN/OUT COM A0 A1 SCL SDA +VDD NC Description Analog Input Channels 0 to 3 Analog Input Channels 0 to 7 Analog Ground Internal Reference/External Reference Input Analog Input Channel Common Slave Address Bit 0 Slave Address Bit 1 Serial Clock Serial Data Power Supply Input. 2.7 to 5.25V. Not Connected
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Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter +VDD to GND Digital Input Voltage to GND Thermal Resistance JA Operating Temperature Range Storage Temperature Range Junction Temperature (TJMAX) ESD 1.5 -40 -65 Min -0.3 -0.3 Max +6 +VDD + 0.3 100 +85 +150 150 Units V V C/W C C C kV HBM MIL-Std. 883E 3015.7 methods The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). on PCB Comments
Package Body Temperature
+260
C
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
Electrical Characteristics
+VDD = +2.7 to +5.25V, VREF = +2.5V external, SCL = 3.4MHz, TAMB = -40 to +85C (unless otherwise specified). Table 3. Electrical Characteristics Symbol Analog Input Parameter Fullscale Input Span Absolute Input Range Negative Input Capacitance ILEAK Leakage Current Static Performance No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match
1 1
Condition Positive input, negative input Positive input
Min 0 -0.3 -0.3
Typ
Max VREF +VDD + 0.3 +VDD + 0.3
Unit V V V pF
Track Mode Hold Mode
15 8 0.1 10 1
A Bits
VREF = 2.5V, 1 LSB = 610V
0.2 0.125 0.025 0.25 0.025 1
0.375 1.5 .5 1.5 0.5
LSB LSB LSB LSB LSB LSB mV
0.125 0.25
Power Supply Rejection Dynamic Performance Throughput Frequency Conversion Time AC Accuracy THD Total Harmonic Distortion Signal-to-Noise Ratio Signal-to-Noise (+ Distortion) Ratio Spurious-Free Dynamic Range Voltage Reference Output Range Internal Reference Drift Output Impedance Quiescent Current Voltage Reference Input Range Input Resistance Reference Input Current PD = 01 Internal Ref. OFF, ADC ON @ 50kSPS 1
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50 6.67 VIN = 2.5VP-P @ 10kHz VIN = 2.5VP-P @ 10kHz VIN = 2.5VP-P @ 10kHz VIN = 2.5VP-P @ 10kHz 2.475 -70 61.5 61.5 70 2.5 30 30 440 VDD 1 4 2.525
kHz s dB dB dB dB V ppm/C A V G A
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics Symbol CMOS Digital I/O VIH VIL VOL IIH IIL Input High Logic Level Input Low Logic Level Output Low Logic Level Input High Leakage Current Input Low Leakage Current 3mA sink current VIH = +VDD VIL = GND Straight binary Specified performance PD = 00 Full Power-Down Analog Current in Static Mode, 3.6V IQSTAT Analog Current in Static Mode, 5.25V PD = 01 Internal Ref. OFF, ADC ON PD = 10 Internal Ref. ON, ADC OFF PD = 11 Internal Ref. ON, ADC ON PD = 00 Full Power-Down PD = 01 Internal Ref. OFF, ADC ON PD = 10 Internal Ref. ON, ADC OFF PD = 11 Internal Ref. ON, ADC ON Quiescent Current at Full Speed, 3.6V IQ Quiescent Current at Full Speed, 5.25V PD = 01 Internal Ref. OFF, ADC ON PD = 11 Internal Ref. ON, ADC ON PD = 01 Internal Ref. OFF, ADC ON PD = 11 Internal Ref. ON, ADC ON 2.7 0.04 400 500 800 0.04 450 550 850 500 850 650 915 5.25 1.2 500 600 900 1.5 550 650 950 600 950 800 1150 A A A A V -1 +VDD x 0.7 -0.3 +VDD + 0.5 +VDD x 0.3 0.4 1 V V V A A Parameter Condition Min Typ Max Unit
Data Format Power Supply Requirements +VDD Power Supply Voltage
1. Guaranteed by design and characterized on sample base. 2. THD measure out to 5th harmonic.
Timing Characteristics
+VDD = +2.7 to 5.25V, TAMB = -40 to +85C (unless otherwise specified). All values referenced to VIHMIN and VILMAX levels. Table 4. Timing Characteristics Parameter SCL Frequency Bus Free Time Between tBUF STOP and START Conditions Hold Time for Repeated THOLDSTART START Condition SCL Low Period tLOW tHIGH SCL High Period Setup Time for Repeated TSETUPSTART START Condition TSETUPDATA Data Setup Time Data Hold Time THOLDDATA TRISESCLK
1 1
Symbol fSCL
Condition
Min 0.1 1.3 160 50 50 100 10
Typ
Max 3.4
Unit MHz s ns
75 75
ns ns ns
70 10 10 40 80
ns ns ns ns
SCL Rise Time SCL Rise Time after Repeated START Condition and After an ACK Bit
TRISESCLK1
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Timing Characteristics Symbol TFALLSCLK TRISESDA TFALLSDA
1 1 1
Parameter SCL Fall Time SDA Fall Time SDA Fall Time STOP Condition Setup Time
Condition
Min 10 20 20 160
Typ
Max 40 80 80
Unit ns ns ns ns
TSETUPSTOP
1. Guaranteed by design and characterized on sample base. Figure 3. Timing Diagram
SDA tBUF tHIGH tHOLDSTART tR tLOW SCL tSETUPDATA tF
tHOLDSTART tSPIKESUP tSETUPSTOP tSETUPSTART
START STOP
tHOLDDATA
Repeated START
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Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VDD = 3.6V; VREF = 2.5V (internal), fSCL = 3.4MHz, CREF = 4.7F, TAMB = +25C (unless otherwise specified). Figure 4. DNL vs. Digital Output Code, Int. Reference Figure 5. INL vs. Digital Output Code, Int. Reference
0,25 0,2 0,15
fSAMPLE = 50ksps
0,375 0,25
fSAMPLE = 50ksps
DNL (LSB) .
0,05 0 -0,05 -0,1 -0,15 -0,2 -0,25 0 256 512 768 1024
INL (LSB) .
0,1
0,125 0 -0,125 -0,25 -0,375 0 256 512 768 1024
Digital Output Code
Digital Output Code
Figure 6. DNL vs. Digital Output Code, Ext. Reference
0,25 0,2 0,15
fSAMPLE = 50ksps
Figure 7. INL vs. Digital Output Code, Ext. Reference
0,375 0,25
fSAMPLE = 50ksps
DNL (LSB) .
0,05 0 -0,05 -0,1 -0,15 -0,2 -0,25 0 256 512 768 1024
INL (LSB) .
0,1
0,125 0 -0,125 -0,25 -0,375 0 256 512 768 1024
Digital Output Code
Digital Output Code
Figure 8. Offset Error vs. Temperature
1,5 1
Figure 9. Offset Matching vs. Temperature
0,5 0,4 0,3
Offset (LSB) .
0,5 0 -0,5 -1 -1,5 -45 -30 -15
Offset (LSB) .
0 15 30 45 60 75 90
0,2 0,1 0 -0,1 -0,2 -0,3 -0,4 -0,5 -45 -30 -15 0 15 30 45 60 75 90
Temperature (C)
Temperature (C)
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Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 10. Offset Error vs. Supply Voltage
1,5 1
Figure 11. Offset Matching vs. Supply Voltage
0,5 0,4 0,3 0,2 0,1 0 -0,1 -0,2 -0,3 -0,4
.
Offset Error (LSB)
0,5 0 -0,5 -1 -1,5 2,7 3,2 3,7 4,2 4,7 5,2
Offset Error (LSB)
.
-0,5 2,7 3,2 3,7 4,2 4,7 5,2
Supply Voltage (V)
Supply Voltage (V)
Figure 12. Gain Error vs. Temperature
1,5 1
Figure 13. Gain Matching vs. Temperature
0,5 0,4
Gain Error (LSB) .
Gain Error (LSB) .
0,3 0,2 0,1 0 -0,1 -0,2 -0,3 -0,4
0,5 0 -0,5 -1 -1,5 -45 -30 -15
0
15 30 45 60 75 90
-0,5 -45 -30 -15
0
15 30 45 60 75 90
Temperature (C)
Temperature (C)
Figure 14. Gain Error vs. Supply Voltage
1,5 1
Figure 15. Gain Matching vs. Supply Voltage
0,5 0,4
Gain Error (LSB) .
Gain Error (LSB) .
2,7 3,2 3,7 4,2 4,7 5,2
0,3 0,2 0,1 0 -0,1 -0,2 -0,3 -0,4
0,5 0 -0,5 -1 -1,5
-0,5 2,7 3,2 3,7 4,2 4,7 5,2
Supply Voltage (V)
Supply Voltage (V)
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Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 16. Supply Current vs. Supply Voltage, PD=00
300 250 200 150 100 50 0 2.7 3.2 3.7 4.2 4.7 5.2
Figure 17. Supply Current vs. Supply Voltage, PD=01
1000
Supply Current (nA) .
Supply Current (A) .
800
600
400
200
0 2.7 3.2 3.7 4.2 4.7 5.2
Supply Voltage (V)
Supply Voltage (V)
Figure 18. Supply Current vs. Supply Voltage, PD=11
1000
Figure 19. Supply Current vs. Sampling Rate, PD = 11
1200 1000 800 600 400 200 0
Supply Current (A) .
800
600
400
200
0 2.7 3.2 3.7 4.2 4.7 5.2
Supply Current (A) .
0
10
20
30
40
50
Supply Voltage (V)
Sampling Rate (ksps)
Figure 20. FFT, Int. Reference
0 -20 -40
fSAMPLE = 50ksps NFFT = 32768
Figure 21. FFT, Ext. Reference
0 -20 -40
fSAMPLE = 50ksps NFFT = 32768
FFT (dBC) .
-80 -100 -120 -140 -160 -180 0 5000 10000 15000 20000 25000
FFT (dBC) .
-60
-60 -80 -100 -120 -140 -160 -180 0 5000 10000 15000 20000 25000
Input Signal Frequency (kHz)
Input Signal Frequency (kHz)
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AS1539/AS1541
Data Sheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1539/AS1541 successive approximation register (SAR) A/D converter architecture is based on capacitive redistribution which inherently includes a sample-and- hold function. The AS1539/AS1541 core is controlled by an internally generated free-running clock. When the device is not performing conversions or being addressed, the A/D converter-core and internal clock are powered off. Figure 22. Simplified I/O Diagram
+2.7 to +5.25V
CH0 VDD CH1 CH2 CH3 CH4 CH5 AS1539 only CH6 CH7 + 0.1 to 10F
0.1 to 10F 2k
+
AS1539/ AS1541
SDA Microcontroller SCL
A0 A1 GND
COM
1F
REFIN/OUT
Analog Input
When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 15pF). After the capacitor has been fully charged, there is no further input current. The amount of charge transfer from the analog source to the converter is a function of conversion rate. Figure 23. Reference circuit
VIN + 1nF +2.7 to +5.25V CH0:CH7 VDD + 0.1 to 10F
10
2k
AS1539
1F REFIN/OUT SDA
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Data Sheet - D e t a i l e d D e s c r i p t i o n
Reference Voltage
The AS1539/AS1541 can operate with an internal 2.5V reference or an external reference. If a +5V supply is used, an external +5V reference is required in order to provide full dynamic range for a 0V to +VDD analog input. The external reference can be as low as 1V. When using a +2.7V supply, the internal +2.5V reference will provide full dynamic range for a 0V to +2.5V analog input. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 1024. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced.
Digital Interface
The AS1539/AS1541 supports the I C serial bus and data transmission protocol in high-speed mode at 3.4MHz. The AS1539/AS1541 operates as a slave on the I C bus. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA. Figure 24. Bus Protocol
2 2
SDA
MSB Slave Address R/W Direction Bit ACK from Receiver ACK from Receiver
SCL
1
2
6
7
8
9 ACK
1
2
3-8
8
9
ACK Repeat if More Bytes Transferred STOP or Repeated START
START
The bus protocol (as shown in Figure 24) is defined as: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. The bus conditions are defined as: - Bus Not Busy. Data and clock lines remain HIGH. - Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. - Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. - Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the I C bus specifications a high-speed mode (3.4MHz clock rate) is defined. - Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge
2
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Data Sheet - D e t a i l e d D e s c r i p t i o n
bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figure 24 on page 11 details how data transfer is accomplished on the I C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: - Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. - Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The AS1539 can operate in the following slave modes: - Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. - Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS1539 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
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Address Byte
The address byte (see Figure 25) is the first byte received following the START condition from the master device. Figure 25. Address Byte
MSB 1 6 0 5 0 4 1 3 0 2 A1 1 A0 LSB R/W
- The first five bits (MSBs) of the slave address are factory-set to 10010. - The next two bits of the address byte are the device select bits, A1 and A0, which are set by the state of pins A1 and A0 at startup. A maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time. Pins A1/A0 can be connected to +VDD or digital ground. - The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is selected; when set to a 0 a write operation is selected. Following the START condition, the AS1539 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
Command Byte
The AS1539/AS1541 operation, including powerdown (see Table 5) and channel selection (see Table 6) is determined by a command byte (see Figure 26). Figure 26. Command Byte
MSB SD 6 C2 5 C1 4 C0 3 PD1 2 PD0 1 X LSB X
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AS1539/AS1541
Data Sheet - D e t a i l e d D e s c r i p t i o n
Where: SD: Single-Ended/Differential Inputs 0: Differential Inputs 1: Single-Ended Inputs C2, C1, C0: Channel Selections PD1, PD0: Power-Down Selection X: Unused
Powerdown Selection
Powerdown modes for the AS1539/AS1541 are selected by setting bits PD0 and PD1 of a command byte (see Command Byte on page 12). Table 5. Powerdown Mode Bit Settings PD1 0 0 1 1 PD0 0 1 0 1 Description Powerdown between A/D converter conversions. Internal reference off and A/D converter on. Internal reference on and A/D converter off. Internal reference on and A/D converter on.
Channel Selection
Channel selection for the AS1539/AS1541 is made using a command byte (see Command Byte on page 12). Table 6. Channel Selection Bit Settings SD 0 0 AS1539 only 0 0 0 0 AS1539 only 0 0 1 1 AS1539 only 1 1 1 1 AS1539 only 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1
CH0 +IN -IN +IN -
CH1 -IN +IN +IN -
CH2 +IN -IN +IN -
CH3 -IN +IN +IN -
CH4 +IN -IN +IN -
CH5 -IN +IN +IN -
CH6 +IN -IN +IN -
CH7 -IN +IN +IN
COM -IN -IN -IN -IN -IN -IN -IN -IN
1. For the 4-channel AS1541 only combinations of CH0:CH3 applies.
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
Initiating a Conversion
After the AS1539/AS1541 has been write-addressed by the bus master, the A/D converter circuitry is powered on, and conversions will begin when a command byte bit C0 (see Command Byte on page 12) is received. If the address byte is valid, the AS1539/AS1541 will return an ACK.
Reading Data
Data can be read from the AS1539/AS1541 by read-addressing the device (LSB of address byte set to 1 (see Command Byte on page 12)) and receiving the transmitted bytes. Converted data can only be read from the AS1539/ AS1541 once a conversion has been initiated as described in Initiating a Conversion. Each 12-bit data word (see Figure 27) is returned in two bytes, where D9 is the MSB of the data word, and D0 is the LSB. Byte 0 is sent first, followed by Byte 1. Figure 27. Data Word
MSB Byte 0 Byte 1 0 D5 6 0 D4 5 0 D3 4 0 D2 3 D9 D1 2 D8 D0 1 D7 0 LSB D6 0
Figure 28 illustrates the interaction between the master and the slave AS1539/AS1541. The most efficient way to perform continuous conversions is to issue repeated STARTs to the AS1539/AS1541 (to secure the bus for subsequent ADC conversions) after reading each conversion. It is recommended that during the conversion mode no data is clocked into the ADC to prevent internal noise. Therefore, after the repeated start commend it is recommanded not to clock in or out any data from the converter for 3.7s. The ADC powers up after the PD0 bit is clocked in and it takes 1.4s to fully power up. At a clock frequency of 3.4MHz this time is automatically achieved and no extra delay should be included. Figure 28. Read Sequence
ADC Powerdown Mode S 1 0 0 1 0 A1 A0 W A ADC Sampling Mode SD C2 C1 C0 PD1 PD0 X X A
Write-Addressing Byte ADC Conversion Mode
Command Byte
ADC Powerdown Mode * 0 1 0 A1 A0 R A 0 0 0 0 D9 D8 D7 D6 A D5 D4 ... D0 0 0 N P
Sr Sampling Instance 3.7s
1
0
Read-Addressing Byte From Master to Slave * Dependant on powerdown selection bits PD0 and PD1 From Slave to Master Use repeated STARTs to secure the bus operation and loop back to the stage of write-addressing for the next conversion.
Where: A: Acknowledge (SDA Low) N: Not Acknowledge (SDA High) S: START Condition P: STOP Condition Sr: Repeated START Condition W: 0 (Write) R: 1 (Read) www.austriamicrosystems.com Revision 1.03 14 - 20
AS1539/AS1541
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Reading with Internal Reference On/Off
The internal reference defaults to off when the AS1539/AS1541 power is on. If the reference (internal or external) is continuously turned on and off, a proper amount of settling time must be added before a normal conversion cycle can be started. The exact amount of settling time needed varies depending on the reference capacitor. For example for a reference capacitor of 4.7F and considering the output impedance of the internal reference of 30 and the amount of time to fully charge the capacitor will be 1.4ms. If the reference capacitor is not fully discharged this time can be reduced greatly. Figure 29 shows the correct internal reference enable sequence before issuing the typical read sequences required for the mode when an internal reference is used. Note: Typical read sequences can be re-used once the internal reference has settled. Figure 29. Internal Reference Enable Sequence and Typical Read Sequence
Internal-Reference Enable Sequence S 1 0 0 1 0 A1 A0 A X X X X 1 X X X A P Internal-Reference Enable Settling Time Wait until required settling time reached
W
Write-Addressing Byte
Command Byte
Typical Mode Read Sequence Settled Internal Reference ADC Powerdown Mode Sr 1 0 0 1 0 A1 A0 A SD C2 C1 C0 1 ADC Sampling Mode PD0 X X A
W
Write-Addressing Byte
Command Byte
Settled Internal Reference ADC Conversion Mode Sr Sampling Instance 1 0 0 1 0 A1 A0 R A 0 0 0 0 ADC Powerdown Mode * D9 D8 D7 D6 A D5 D4 ... D0 D0 D0 N P **
Read-Addressing Byte
2 x (8-bits +ACK/NACK
From Master to Slave
* Dependant on powerdown selection bits PD0 and PD1. ** To remain in HS mode, use repeated STARTs instead of STOPs
From Slave to Master
Where: A: Acknowledge (SDA Low) N: Not Acknowledge (SDA High) S: START Condition P: STOP Condition Sr: Repeated START Condition W: 0 (Write) R: 1 (Read) X: Dont Care
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AS1539/AS1541
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
When using the internal reference: 1. Bit PD1 off the command byte must always be set to logic 1 for each sample conversion that is issued by the sequence, as shown in Figure 28 on page 14. 2. In order to achieve 10-bit accuracy conversion when using the internal reference, the internal reference settling time must be considered. If bit PD1 has been set to logic 0 while using the AS1539/AS1541, then the settling time must be reconsidered after PD1 is set to logic 1 (i.e., whenever the internal reference is turned on after it has been turned off, the settling time must be long enough to get 10-bit accuracy conversion). 3. When the internal reference is off, it is not turned on until both the first command byte with PD1 = 1 is sent and then a STOP condition or repeated START condition is issued. (The actual turn-on time occurs once the STOP or repeated START condition is issued.) Any command byte with PD1 = 1 issued after the internal reference is turned on serves only to keep the internal reference on. Otherwise, the internal reference would be turned off by any command byte with PD1 = 0. The example in Figure 29 can be generalized for a conversion cycle by simply swapping the timing of the conversion cycle. Note: If an external reference is used, PD1 must be set to 0, and the external reference must be settled. The typical sequence in Figure 28 on page 14 or Figure 29 on page 15 can then be used.
Layout
For optimum performance, care should be taken with the physical layout of the AS1539/AS1541 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. - Power to the AS1539/AS1541 should be clean and well-bypassed. A 0.1F ceramic bypass capacitor should be placed as close to the device as possible. A 1 to 10F capacitor may also be needed if the impedance of the connection between +VDD and the power supply is high. - The AS1539/AS1541 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. - While high-frequency noise can be filtered out, voltage variation due to line frequency (50 or 60Hz) can be difficult to remove. - The GND pin should be connected to a clean ground point. In many cases, this will be the analog ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. - The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. Note: For additional information download the evaluation board application note on our website.
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Revision 1.03
16 - 20
AS1539/AS1541
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
Figure 30. TSSOP-16 Package
Notes: 1. All dimensions are in millimeters; angles in degrees. 2. Dimensioning and tolerancing per ASME Y14.5M - 1994. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0.15mm per side. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 6. Terminal numbers are for reference only. 7. Datums A and B to be determined at datum plane H. 8. Dimensions D and E1 are to be determined at datum plane H. 9. This dimension applies only to variations with an even number of leads per side. 10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
Symbol A A1 A2 L R R1 b b1 c c1 1 L1 aaa bbb ccc ddd e 2 3 D E1 E e N
Typ 0.90 0.60 0.22 1.0REF 0.10 0.10 0.05 0.20 0.65BSC 12REF 12REF Variations 4.90 5.00 4.30 4.40 6.4BSC 0.65BSC 16
Min 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0
Max 1.10 0.15 0.95 0.75 0.30 0.25 0.20 0.16 8
Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2,5 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3,8 1,2,4,8 1,2 1,2 1,2,6
5.10 4.50
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Revision 1.03
17 - 20
AS1539/AS1541
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 31. TQFN 4x4 16-pin Package
Symbol A A1 L L1 K aaa bbb ccc ddd
Min 0.70 0.00 0.45 0.03 0.20
Typ 0.75 0.02 0.55
Max 0.80 0.05 0.65 0.15
0.10 0.10 0.10 0.05
Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
Symbol D BSC E BSC D2 E2 b e N ND
Min
2.00 2.00 0.25
Typ 4.00 4.00 2.15 2.15 0.30 0.65 16 4
Max
2.25 2.25 0.35
Notes 1, 2 1, 2 1, 2 1, 2 1, 2, 5 1, 2 1, 2, 5
Notes: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All dimensions are in millimeters, angle is in degrees. N is the total number of terminals. Terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the area indicated. The terminal #1 identifier may be either a mold, embedded metal or mark feature. 5. Dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. 6. ND refers to the maximum number of terminals on D side. 7. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.
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Revision 1.03
18 - 20
AS1539/AS1541
Data Sheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The device is available as the standard products shown in Table 7. Table 7. Ordering Information Model AS1539-BTST AS1539-BTSU AS1541-BQFT Marking AS1538 AS1538 AS1540 Description 8-Channel, 10-Bit IC Analog-to-Digital Converter 8-Channel, 10-Bit IC Analog-to-Digital Converter 4-Channel, 10-Bit IC Analog-to-Digital Converter Delivery Form Tape and Reel Tubes Tape and Reel Package TSSOP-16 TSSOP-16 TQFN 4x4 16-pin
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Revision 1.03
19 - 20
AS1539/AS1541
Data Sheet
Copyrights
Copyright (c) 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
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Revision 1.03
20 - 20

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